The present invention relates to a multi-layered structure and a method of fabricating the structure, and to a semiconductor device fabricated using the multi-layered structure and a method of fabricating the semiconductor device. In particular, the present invention concerns a multi-layered structure having an ultra-thin single crystalline semiconductor film formed on an insulator and a method of fabricating the structure, and an MOS transistor and a bipolar transistor formed using the ultra-thin single crystalline semiconductor layer, and a method of fabricating these transistors.
The structure shown in FIG. 2 is well-known in a single crystalline Si layer 3 is formed on a supporting substrate (Si substrate) 1 by way of an insulator 2. This is generally called an SOI (Silicon on Insulator) substrate. The SOI substrate is fabricated by the steps of implanting highly concentrated oxygen ions on the surface region of the Si substrate 1 for forming silicon dioxide, and recovering crystal defects near the surface for single crystallization and enhancing the quality of a buried oxide film 2 by heat-treatment at a high temperature.
Alternatively, the SOI substrate is fabricated by the steps of directly bonding a second single crystalline Si substrate 3 to a silicon dioxide film 2 formed on a single crystalline Si substrate 1 without any adhesive, and then grinding and polishing the second Si substrate 3 from the rear surface side for thinning the thickness of the second Si substrate 3, thereby forming a structure in which the silicon dioxide film 2 is buried under the thin single crystalline Si film 3.
In this way, an SOI substrate, in which an ultra-thin single crystalline semiconductor layer having a thickness of 100 to 200 nm is formed on an insulator, can be formed. Such an SOI substrate has been practically used as a substrate for an ultra-thin SOI (Silicon On Insulator) MOS transistor. In the ultra-thin SOI MOS transistor using this SOI substrate, a source/drain junction can be directly formed on a thick buried oxide film, so that a source/drain stray capacitance can be reduced to be half or less that of the conventional one. The gate capacitance and the metallization stray capacitance can be also significantly reduced by the effect of the buried oxide film, thus enabling the operation of the transistor to be performed at an increased speed. Moreover, the fabrication method can be significantly simplified using the SOI substrate, for example, a well formation process can be eliminated, so that the fabrication cost can be significantly reduced.
A bipolar transistor using the SOI (Silicon On Insulator) substrate, as shown in FIG. 3, is also well-known. In FIG. 3, numeral 1 designates a supporting substrate made of a single crystalline silicon (Si); 2 is a silicon oxide film; and 3 is an SOI layer made of a single crystalline silicon (in this specification, a single crystalline semiconductor layer formed on an insulator is referred to as the SOI layer).
An n-type highly concentrated collector region 4 is selectively formed within the SOI layer 3, and a thin single crystalline silicon layer is formed on the main surface of the SOI layer 3 by a known epitaxial growth process. In FIG. 3, numeral 5 designates a region separation insulator, 6 is a device isolation insulator, 7 is a field oxide, and 8 is a p-type intrinsic base region; all are formed on the above single crystalline silicon layer. Moreover, numeral 9 designates a base leadout electrode, 10 is an electrode protection insulator, 11 is an emitter-base separation insulator, 12 is a base leadout electrode, 13 is a graft base region, which are formed by diffusion of impurities from the base leadout electrode 9. Numeral 15 designates an emitter region, and 16, 17 and 18 are emitter, base, and collector metal electrodes, respectively.
The transistor shown in FIG. 3, which is perfectly separated from the silicon substrate 1 by the insulator 2, has features to reduce the collector-substrate capacitance thereby increasing the operation speed, and to prevent error in circuit operation and noise due to charge generated in the substrate by .alpha.-ray irradiation.
In the structure shown in FIG. 3, the film thickness of the SOI layer 3 is generally made to be as thick as 1 .mu.m or more for sufficiently lowering the resistance of the collector region 4; accordingly, the SOI layer in this structure is different from that used for the ultra-thin SOI MOS transistor.
The MOS transistor is suitable for forming a micro-structure, that is, for achieving high integration when compared to the bipolar transistor, but is not suitable for high speed operation because the drivability is inferior to that of the bipolar transistor. For realizing a large scale integration circuit of high speed and high integration, a circuit having the MOS transistor combined with the bipolar transistor has been extensively used, and is called a BiCMOS circuit. In this case, by forming the MOS transistor within the thin SOI layer, it becomes possible to improve the drivability by the effect of reducing the stray capacitance. However, this is not sufficient yet in the high speed performance as a high speed semiconductor device used for a large size computer.
If the BiCMOS circuit is formed within the thin SOI layer, it becomes possible to realize a large scale integrated circuit which has excellent combined characteristics of both an MOS transistor capable of further enhancing the integration and a bipolar transistor being excellent in the drivability and capable of achieving the high speed operation, and hence to improve the performance of a large size computer or the like.
A technique of fabricating a bipolar transistor within a thin SOI layer has been disclosed by the present inventors in Unexamined Japanese Patent Publication No. HEI 3-130977. However, a bipolar transistor described in this document is the so-called lateral transistor in which an emitter, a base and a collector are disposed in the lateral direction, and the base width is determined by the minimum future size and the condition of impurity diffusion. Although the base width can be controlled to be 50 nm or less using the recent impurity diffusion technique, the minimum future size by etching, which is dependent on the exposing method, is substantially limited to several hundred nm, with a large variation.
On the other hand, the vertical transistor, in which an emitter, a base and a collector are disposed in the vertical direction, has been improved in the performance by thinning the width of an intrinsic collector, the base width and the like, and thereby realized the high speed operation. In this vertical transistor, however, it has been difficult to extremely lower the lateral dimension because of a limitation in fabrication of a micro-structure, and hence to further improve the high speed operation.
Therefore, according to the prior art methods, it has been difficult to fabricate an MOS transistor having an ultra-high integration density and a vertical bipolar transistor enabling a high speed operation within the same thin SOI layer.